A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology
نویسندگان
چکیده
منابع مشابه
A wide-range all-digital duty-cycle corrector with output clock phase alignment in 65nm CMOS technology
A wide-range all-digital duty-cycle corrector (ADDCC) with output clock phase alignment is presented in this paper. The proposed ADDCC can correct the duty-cycle error of the input clock to 50% duty-cycle. The acceptable duty-cycle range and frequency range of input clock is from 20% to 80% and from 250MHz to 1GHz, respectively. The proposed ADDCC is implemented on a standard performance 65 nm ...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2011
ISSN: 1349-2543
DOI: 10.1587/elex.8.1245